qbaylogic.com

What It Is

QBayLogic is a steward-owned FPGA/ASIC design house that originated as a University of Twente spin-off. It is not positioned as a typical SaaS product, but rather as a provider of engineering services and methodologies for digital hardware R&D. Its core work is helping customers implement complex algorithms as high-throughput, low-latency, low-power FPGA or ASIC solutions, with applications spanning embedded systems, edge computing, data centers, communications, sensors, cryptography, and defense-related systems.

Core Capabilities and Tech Stack

Its services cover FPGA design, Digital ASIC design, FPGA/ASIC verification, workflow design/buildout, and Clash training. The website explicitly mentions traditional RTL capabilities in VHDL and Verilog, while also emphasizing the use of Clash: an open-source compiler written in Haskell that converts high-level Haskell code into low-level HDL. For verification, QBayLogic uses CoCoTB, Python, Hedgehog, Hypothesis, and bounded model checking, and is familiar with QuestaSim, Verilator, and Xcelium. On the engineering workflow side, it can set up GitLab CI, GitHub Actions, and Jenkins, supporting automated testing, synthesis, place-and-route, nightly builds, and caching.

Pricing and Delivery

The website does not disclose standard pricing, packages, payment methods, or SLA terms. Based on the description, it appears to operate more like a project-based consulting and delivery service. Clash training can also be customized from a one-day workshop to multi-day courses. Before procurement, customers need to contact the company directly to confirm quotes, timelines, intellectual property ownership, and maintenance arrangements.

Pros and Cons

The main advantages are its comprehensive vertical FPGA/ASIC capabilities: it can handle everything from RTL to GDSII, as well as verification, CI, and team training. It also has experience with high-speed interfaces such as HBM, DDR3/4, PCIe, SERDES, and 10G/25G/40G Ethernet. Its open-source Clash expertise gives it differentiation in high-level hardware design. The downsides are the lack of commercial information, and the fact that the Clash/Haskell approach has a learning curve for teams used to traditional Verilog/VHDL. It is also not an out-of-the-box developer tool platform.

Who It’s For and Access from China

QBayLogic is best suited for enterprise R&D teams with clear needs around hardware acceleration, low latency, and deterministic real-time processing, such as teams working in communications, industrial control, data centers, sensor arrays, cryptographic systems, and ASIC verification. The source text does not provide details on access from China, and payment methods are also unknown. If network access or procurement is restricted, alternatives may include local FPGA/ASIC design service providers, EDA consulting teams, or internal toolchains based on Verilog/VHDL/SystemVerilog, Chisel, SpinalHDL, or HLS.