piplin.org

What It Is

Piplin is an FPGA-oriented developer tool/language that lets users simulate and write hardware logic in Clojure, then generate synthesizable Verilog. It is not positioned as a simple replacement for traditional HDLs; instead, it aims to use Clojure’s functional abstraction capabilities to raise the organization, reuse, and composition of hardware modules to a higher level.

Core Capabilities

Functionally, Piplin’s key value is “write hardware in Clojure, output Verilog.” The main text explicitly states that it can generate synthesizable Verilog understood by all FPGA toolchains, and that it supports higher-level data and computation constructs such as maps, enums, tagged unions, and fixed point math. Developers can organize code with namespaces, reuse computational logic through functions, and compose hardware functionality with higher-order functions.

For modularity, Piplin uses Prismatic’s Plumbing graphs to combine functions and registers into modules, which is its abstraction for composable stateful hardware. On the testing side, it supports hardware simulation, produces results that are easy to understand and test, allows simulation results to be inspected via waveform diagrams, and can automatically compare simulations against the Verilog implementation to verify compiler correctness.

Pricing and Open Source

The main text does not mention any commercial pricing, subscriptions, or enterprise edition. The website provides a “Code on Github” entry point, indicating that the code can be viewed on GitHub, but the crawled content does not show a license, so the specific open-source license cannot be confirmed. There is also no information about payment methods, commercial support, or SLAs.

Pros and Cons

Its strengths are its powerful abstraction capabilities, making it suitable for developers familiar with Clojure who want to write FPGA logic using more modern software engineering approaches. It can also generate Verilog, making it compatible with existing FPGA toolchains, and it places emphasis on simulation and verification. The drawbacks are its clearly high learning curve: users need to understand both Clojure and hardware design. The main text also lacks information about maintenance status, ecosystem size, installation requirements, licensing, and versioning, so further validation is needed before adopting it in an engineering workflow.

Who It’s For and Access from China

Piplin is better suited to research teams, FPGA engineers, hardware DSL enthusiasts, and people who want to use functional programming to abstract hardware modules. If a team primarily relies on a traditional Verilog/SystemVerilog workflow, migration costs may be relatively high. The main text provides no information about access from China, so its accessibility is unknown. If access to GitHub or related resources is unstable, alternatives to consider include Chisel, SpinalHDL, Migen, Amaranth HDL, or traditional HDLs.