openasip.org

What it is

OpenASIP (formerly TCE) is an open application-specific instruction-set processor toolset led by the Customized Parallel Computing group at Tampere University in Finland. It targets compiler-programmable accelerator design, with its core based on the energy-efficient Transport Triggered Architecture (TTA) processor template. Since version 2.0, it has also supported co-design with the RISC-V instruction set.

Core features and ecosystem

OpenASIP provides a complete retargetable co-design flow, from high-level language programs to synthesizable processor RTL and parallel program binaries. Customizable elements include register files, function units, supported operations, and interconnect networks. The compiler is based on LLVM, uses Clang as the default frontend, and supports OpenCL via pocl. The backend supports VHDL, while Verilog support remains experimental. For simulation, it offers both graphical and command-line interfaces, with support for cycle-by-cycle debugging, fast static compiled simulation, and dynamic compiled simulation. For system integration, it includes capabilities such as a SystemC API, IP-XACT 1.5, FPGA platform integration file generation, and program bit image generation.

Documentation, pricing, and openness

The main documentation explicitly describes it as an open toolset and provides download and installation instructions, but it does not list a specific license or commercial pricing. Its documentation set is fairly complete, including a user manual PDF, Doxygen API documentation, ADF/TPEF file format specifications, tutorial slides, and exercise materials, making it suitable for research and teaching. However, the content is academic and low-level engineering oriented, so newcomers are expected to have a foundation in processor architecture, compilers, and hardware description languages.

Pros, cons, and who it is for

Its main strength is that it covers the full ASIP design flow and connects with ecosystems such as LLVM, RISC-V, OpenCL, SystemC, and VHDL/Verilog. It is well suited to exploring custom instructions, function units, and interconnect design spaces. The downsides are its high learning curve, the fact that Verilog support is still experimental, and examples showing that extremely optimized architectures may make it difficult for a C compiler to generate efficient code, requiring hand-written processor code. It is better suited to universities, research institutions, chip architecture teams, and FPGA/ASIC accelerator developers than to general software development teams.

Access from China and alternatives

The main content does not provide information on mainland China access, mirrors, payment, or commercial procurement, so its accessibility status is unknown. If access is unstable, options include installing from local source code, using academic networks, or looking for relevant mirrors. Alternative directions include RISC-V custom extension toolchains, Vitis HLS, traditional HLS/EDA tools, and other ASIP/CGRA research platforms.