cogarch-workshop.org

What It Is

CogArch Workshop is an academic workshop focused on cognitive architectures and AI system architecture. This edition will be co-located with the 53rd International Symposium on Computer Architecture (ISCA 2026) at the Raleigh Convention Center in the United States. It is not a conventional online course, but a research-oriented event built around abstract submissions, research talks, prototype demos, invited presentations, and panel discussions.

Core Topics and Format

Judging from the call for papers, this edition focuses on architectural challenges as large models scale from a single chip to multi-chip and multi-node clusters, with particular attention to how collective communication patterns such as AllReduce, AllGather, and ReduceScatter affect training and inference performance. Topics include 2.5D/3D chiplets, advanced packaging, cluster networks, compilers and runtimes, memory and I/O hierarchies, energy efficiency, reliability, security, and AI-driven modeling tools for communication optimization. The language of instruction and discussion is English. Submissions are limited to a maximum 2-page English abstract, and participants may choose between a regular presentation or a prototype demo.

Instructors and Institutional Background

The organizers are all from IBM T. J. Watson Research Center, including Pradip Bose, Alper Buyuktosunoglu, Karthik Swaminathan, and Augusto Vega. Their backgrounds span high-performance, reliability-aware, and power-aware architecture; IBM Power/z Systems; domain-specific accelerators; cognitive computing; and embedded design. Overall, both the institution and organizing team have a strong industrial research profile.

Pricing and Registration

The page does not provide specific pricing, early-bird rates, or student ticket information. It only states that CogArch will be co-located with ISCA 2026 and that participants should refer to the main conference registration. As a result, fees, payment methods, and refund/change policies cannot be confirmed from the current text. For attendees from China, additional costs such as international conference registration, travel, visas, and foreign-currency payments should also be considered.

Pros, Cons, and Who It’s For

Its strengths lie in its forward-looking and tightly focused themes. It is well suited to researchers working on large-model systems, chiplet interconnects, distributed training, compiler/runtime systems, and hardware/software co-design. Authors of accepted submissions may also be invited to submit a full-length version to an IEEE Micro special issue on GenAI and Chiplets. The limitations are that it is not a structured course, and there is no clear syllabus, certificate, or recorded content. Speakers and the schedule have not yet been announced, and the barrier to entry is relatively high for general learners.

Access from China and Alternatives

Whether the website is accessible from mainland China cannot be determined from the text alone, so its status should be considered unknown. If the main goal is learning, good alternatives include university courses on computer architecture, AI systems, chip interconnects, and parallel computing. If the goal is academic exchange, consider following ISCA, MICRO, HPCA, ASPLOS, and their related workshops. Within China, relevant events from the China Computer Federation and university research groups in computer architecture are also worth watching.